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< VHDL for FPGA Design
VHDL Implementation Of 16 Bit ALU Prof. Ravindra Joshi 1, Nagesh Naik 2, Nilesh Kashid 3, Sneha Waykar 4, Chirag Rangrass 5 Department of Electronics and Telecommunication KCCEMSR, Thane, India [email protected] Abstract — In this paper VHDL implementation of 16 Bit ALU is proposed to be implemented. With help of 5 select lines, it.
4-Bit ALU VHDL Code[edit]
A combinatorial ALU with the following operations:
Operation | Result | Flag | Description |
---|---|---|---|
000 | Nibble1 + Nibble2 | Carry = Overflow | Addition |
001 | | Nibble1 - Nibble2 | | 1 if Nibble2 > Nibble1, 0 otherwise | Test / diff |
010 | Nibble1 AND Nibble2 | 0 | Bitwise AND |
011 | Nibble1 OR Nibble2 | 0 | Bitwise OR |
100 | Nibble1 XOR Nibble2 | 0 | Bitwise XOR |
101 | 15 - Nibble1 | 0 | Bitwise inverse of Nibble1 |
110 | 15 - Nibble2 | 0 | Bitwise inverse of Nibble2 |
111 | Nibble1 + Nibble2 + 1 | Carry = Overflow | Addition |
Simulation Waveform[edit]
Generated Symbol[edit]
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